Latency control circuit and method of latency control

摘要

The memory device includes a memory cell array, and an output buffer receiving data addressed from the memory cell array and outputting the data based on a latency signal. A latency circuit selectively associates a plurality of transfer signals with a plurality of sampling signals based on a CAS latency to create a desired timing relationship between each sampling signal and the associated transfer signal. The latency circuit stores read information in accordance with at least one of the plurality of sampling signals, and generates a latency signal based on the transfer signal associated with the sampling signal used in storing the read information.