发明名称 Memory-to-memory copy and compare/exchange instructions to support non-blocking synchronization schemes
摘要 A coherency technique for multiprocessor systems in which threads perform atomic read or atomic write transactions pursuant to memory-to-memory copy instructions or memory-to-memory compare-and-exchange instructions. Although the source reads and target writes are each atomic, the instruction is not required to be atomic from the read through the write operation. Accordingly, once a first thread reads source data pursuant to a read, for example, it may allow other threads to access that data prior to completing its own target write. The data may include a version stamp. After the first thread operates on the data, software may read in the version stamp a second time. If the two version stamps agree, the results of the thread's operation may be considered valid for lookup operations. For a compare and exchange operation, a thread may read data from a source location. Subsequently, the thread may read atomically a current copy of a version stamp from a target address, compare it to a version of the same version stamp obtained earlier, and, if the two version stamps agree, write the source data to the target address.
申请公布号 US6708256(B2) 申请公布日期 2004.03.16
申请号 US20020230288 申请日期 2002.08.29
申请人 INTEL CORPORATION 发明人 ZAHIR ACHMED RUMI
分类号 G06F9/46;G06F12/02;G06F12/08;G06F12/14;(IPC1-7):G06F12/00 主分类号 G06F9/46
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