Clock generator, clock generating method, and signal receiver

摘要

A selector 203 selects two frequency-dividing number data items. One of the data items represents at least one integral frequency-dividing number greater than a ratio (fa/fb) of the frequency (fa) of an input clock signal to the frequency (fb) of a target output clock signal. The other data item represents at least one integral frequency-dividing number smaller than the ratio (fa/fb). A frequency-division counter 204 divides the frequency of the input clock signal by the frequency-dividing number represented by the frequency-dividing number data items selected by the selector 203. A select data generator 205 generates selection data in accordance with the frequency data representing the target frequency (fb). The selection data causes the selector 203 to select the frequency-dividing number data items repeatedly, thereby to divide the frequency of the input clock signal, so that the average frequency of the output clock signal generated by the frequency-division counter 204 may equal the target frequency (fb).