| 摘要 |
Methods and apparatuses for concatenating codewords of variable lengths using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to concatenate codewords of variable lengths includes: receiving a plurality of codewords from a first vector register; receiving a plurality of lengths representing bit lengths of the plurality of codewords respectively; generating a first bit stream from concatenating the plurality of codewords; summing the plurality of lengths to generate the bit length of the first bit stream; and outputting the first bit stream and the first length; wherein the above operations are performed in response to the microprocessor receiving a single instruction.
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