| 摘要 |
At one of main surfaces of a silicon substrate serving as an N+type drain region is arranged an N type first high resistance drift layer. On the first high resistance drift layer is arranged an N-type second high resistance drift layer. A P- type high resistance buried layer is arranged on the surface layer of the first high resistance drift layer and the bottom layer of the second high resistance drift layer at a position right under each of a plurality of P type base regions arranged on the surface layer of the second high resistance drift layer. The thickness T1 of the first high resistance drift layer is set in such a manner that a depletion layer extending over the first high resistance drift layer reaches through the drain region at a voltage lower than a sharing voltage V1 shared by the first high resistance drift layer. |
