| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory command having no register, an address system, and a memory module, capable of operating not only at the time of 266 MHz CLK (clock) but also at the time of 200 MHz CLK. SOLUTION: A clock signal having a good signal integrity is supplied to a DRAM2 through a PLL (phase locked loop) circuit 3 mounted on a module 1. Send-out timing of a CA (command/address) single from a chip set or timing of a clock signal CLKd supplied to the DRAM2 by the PLL circuit 3 is controlled. Margins of a set-up time and a holding time of the CA single to the clock signal CLKd in the DRAM2 are made to be equal, and 266 MHz CLK operation is also enabled. When used at both of 266 MHz and 200 MHz, by using 3750 ps equivalent to the timing of the CA signal from the chip set 1 or the timing of the clock signal CLKd is controlled. Even at the time of 200 MHz, the minimum margin is ensured to be equal to or better than when it is 266 MHz, so that only one kind of the module is required. COPYRIGHT: (C)2004,JPO
|
