| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which operation speed of an operation cycle can be increased and to provide its control method. <P>SOLUTION: This device is provided with a means receiving a command signal and generating a signal (RPB) for read-control based on transition of a clock signal CLK and means receiving a command signal and generating a signal (WPB) for write-control based on transition of a clock signal. decoding of an address, selection of a word line, and activation of a sense amplifier are performed based on the signal for read-control, decoding of an address, selection of a word line, and activation of a write-amplifier are performed based on a read-cycle in which cell data is read out and the signal for write-control, writing data in a selected cell is performed, further, a write-cycle in which pre-charge of a bit line is performed and the above are performed alternately, and a decoding period of the read-cycle and a sense period are overlapped. <P>COPYRIGHT: (C)2004,JPO |
