| 摘要 |
A timing circuit has a bit line isolation signal input from one input terminal, and controls a timing to output the bit line isolation signal to a memory mat using an external signal input from the other input terminal. Thus, by controlling an operation timing of the bit line isolation signal with the external signal, an effect of a short circuit of a word line and a bit line caused on one memory cell array will be communicated also to the other memory cell array, and a defective bit line on the opposite sides of a shared sense amplifier can be detected.
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