发明名称 Advanced encryption standard hardware accelerator and method
摘要 A method of performing encryption and decryption includes implementing a block cipher algorithm, generating encryption and decryption round keys for an accelerator module, and implementing the accelerator module using shared logic for one or more round key sizes, wherein the decryption uses a stored expanded key word to initialize subsequent block decryptions. The block cipher algorithm can be the Rijndael algorithm. Only a first block decryption requires expansion overhead. All subsequent block decryptions utilize a prior key to initialize a key expansion engine for a plurality of subsequent blocks. The subsequent block decryptions are performed at a same rate as block encryptions. An apparatus includes a plurality of logic gates configured to reuse expanded round keys from a prior decryption round, the logic gates complete one round of data decryption per clock cycle after an initial round of data decryption, and a plurality of decoders configured to convert the decrypted data to usable data.
申请公布号 US2004047466(A1) 申请公布日期 2004.03.11
申请号 US20020236806 申请日期 2002.09.06
申请人 FELDMAN JOEL;TKACIK THOMAS 发明人 FELDMAN JOEL;TKACIK THOMAS
分类号 H04L9/06;H04L9/10;(IPC1-7):H04K1/04;H04K1/06 主分类号 H04L9/06
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