| 摘要 |
PROBLEM TO BE SOLVED: To improve reliability by mitigating field convergence between wirings caused by the fineness thereof. SOLUTION: Bit lines BL1e, BL1o, and BL2e, BL2o of a wiring layer M1 are arranged to have smallest widths and smallest spaces in a chip, and a potential difference V1 at the maximum is imparted between the bit lines. The smallest space is provided with a value that causes no short circuit due to dielectric breakdown when the potential difference V1 is imparted between the bit lines. This value may be of the smallest machining dimension by design rule or lithography. A potential difference V2 (>V1) is imparted between a shield power wire BLSHIELD and the bit lines in the wiring layer M1, while the shield power wire BLSHIELD is sufficiently distanced from a region where the bit lines are arrayed at the smallest spaces. COPYRIGHT: (C)2004,JPO
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