发明名称 METHOD FOR REDUCING POWER CONSUMPTION IN A STATE RETAINING CIRCUIT, STATE RETAINING CIRCUIT AND ELECTRONIC DEVICE
摘要 A method for reducing the power consumption in a state retaining circuit during a standby mode is disclosed comprising, in an active state, providing a regular power supply (VDD) and a standby power supply (VDD STANDBY) to the state retaining circuit; for a transition from an active state to a standby state, decreasing the regular power supply to ground level and maintaining the standby power supply (VDD STANDBY) thus providing the circuit elements (36, 142, 78, 85) of the state retaining circuit with enough power for retaining the state during standby mode; and for a transition from the standby state to the active state, increasing the regular power supply (VDD) from its ground level to its active level. A circuit for reducing the power consumption in a state retaining circuit during a standby mode is disclosed comprising a control unit (1) providing at least one control signal; a data input unit (3) providing at least one input signal; a data output unit (7) providing at least one output signal; a data storage unit (5) for holding the state of the circuit during an a standby mode; a regular power supply supplying power to the data storage unit (5) during an active mode; and a standby power supply supplying power to at least a part of the data storage unit (5) during the active mode and the standby mode.
申请公布号 WO2004021351(A1) 申请公布日期 2004.03.11
申请号 WO2003IB03418 申请日期 2003.08.04
申请人 KONINKLIJKE PHILIPS ELECTRONICS N.V.;GARG, MANISH;RAO, KIRAN, B., R.;PINEDA DE GYVEZ, JOSE, D., J. 发明人 GARG, MANISH;RAO, KIRAN, B., R.;PINEDA DE GYVEZ, JOSE, D., J.
分类号 G11C11/41;G11C5/14;H03K3/356 主分类号 G11C11/41
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