| 摘要 |
The invention relates to an electrically erasable programmable memory which is integrated onto a silicon substrate, comprising a memory area consisting of normal bit lines (BLj) and normal memory cells (C(i, j)) which are connected to the aforementioned normal bit lines (BLj). Each normal memory cell consists of a floating gate transistor (FGT) comprising a tunnel window (TW) and a selection transistor (ST). According to the invention, the memory area (MA) includes at least one memory point of a non-volatile register (NVREG), comprising: a normal memory cell (C(i+1, j) which is connected to a normal bit line (BLj) of the memory area and which can be erased and programmed using decoders (RDEC, CDEC) of the memory area; a special memory cell C(i+1, j+1) comprising a floating gate transistor (FGT) without a tunnel window, the floating gate of the floating gate transistor of the special memory cell being connected to the floating gate of the floating gate transistor of the normal memory cell; and a special bit line (RBL+1) which is used to connect the special memory cell of the memory point to a specific read-out circuit of the memory point. |
