发明名称 INSTRUCTION SCHEDULING METHOD, INSTRUCTION SCHEDULING DEVICE, AND PROGRAM
摘要 PROBLEM TO BE SOLVED: To provide an instruction scheduling method and device for arranging instructions in fewer clock cycles than a conventional method. SOLUTION: A data dependency analyzer 140 generates a data dependence graph indicating the data dependency of each instruction acquired from an assembler code generator 120. A precedence constraint ranking calculation part 151 calculates precedence constraint ranking by weighting and accumulating each arc of the graph. When two resource-constrained instructions of the same precedence constraint ranking calculated and being under data dependency are not processed in parallel because of the resource constraint, a resource constraint ranking evaluation part 152 raises the precedence constraint ranking of the preceding instruction. A priority ranking calculation part 150 considers the raised precedence constraint ranking as the priority ranking, an instruction selection part 161 selects the instruction of the top priority ranking, and an execution time determination part 160 repeats the processing of arranging the selected instruction till all the instructions are arranged. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004078824(A) 申请公布日期 2004.03.11
申请号 JP20020241877 申请日期 2002.08.22
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 OGAWA HAJIME;HEIJI TAKEHITO;TAKAYAMA SHUICHI;SAKATA TOSHIYUKI;DOMOTO SHOHEI
分类号 G06F9/45;(IPC1-7):G06F9/45 主分类号 G06F9/45
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