发明名称 DATA TRANSMISSION/RECEPTION SYSTEM
摘要 <p>When a clock signal and a plurality of data signals synchronized with the clock signal are transferred, a clock transmission system (12) feedback-controls the driver switch drive pulse width so that the clock signal is transmitted with a small amplitude and the control signal of the pulse width is used for controlling the driver switch in each data transmission system (13), thereby simultaneously realizing small amplitude transmission of each data signal. Furthermore, a clock reception system (10) applies the control signal of the aforementioned pulse width to delay control of a clock delay circuit, so as to realize an optimal latch timing of reception data in each data reception system (11).</p>
申请公布号 WO2004021656(A1) 申请公布日期 2004.03.11
申请号 WO2003JP10884 申请日期 2003.08.27
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.;DOSHO, SHIRO;TOKUNAGA, YUSUKE;DOI, YASUYUKI;NAKAGAWA, HIROFUMI;DATE, YOSHITO;OHMORI, TETSURO;NISHIKAWA, KAORI 发明人 DOSHO, SHIRO;TOKUNAGA, YUSUKE;DOI, YASUYUKI;NAKAGAWA, HIROFUMI;DATE, YOSHITO;OHMORI, TETSURO;NISHIKAWA, KAORI
分类号 G09G3/36;H04L25/02;H04L25/49;(IPC1-7):H04L25/02;H04L25/40 主分类号 G09G3/36
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