发明名称 VERTICAL SYNCHRONIZING SIGNAL PROCESSING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To solve the problem that a field is erroneously discriminated when the change point of vertical synchronizing signals shifts from an estimated timing by 25% of one line or more in forming the window of 25% to 75% of 1H and discriminating the field depending on whether or not horizontal synchronizing signals are present in the window. SOLUTION: A normal mode, a special mode and a non-signal mode are discriminated in a mode discrimination circuit 29 by using the window generated in a window generation circuit 28. When the discriminated result is the special mode, the next field is predicted on the basis of past field information by a field information generation circuit 30, a processing corresponding to the field is executed in a corrected vertical synchronizing signal generation circuit 31, and corrected vertical synchronizing signals (corrected vres) are generated. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004080590(A) 申请公布日期 2004.03.11
申请号 JP20020240278 申请日期 2002.08.21
申请人 SONY CORP 发明人 NAGATSUMA TOSHIYUKI
分类号 H04N5/10;H04N5/06;(IPC1-7):H04N5/10 主分类号 H04N5/10
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