METHOD AND APPARATUS FOR SETTING AND COMPENSATING READ LATENCY IN A HIGH SPEED DRAM

摘要

An apparatus and method for coordinating the variable timing of internal clock signals derived from an external clock signal to ensure that read data and a read clock used to latch the read data arrive at the data latch in synchronism and with a specified read latency. A read clock (129) is produced from the external clock signal (116) in a delay lock loop circuit (120) and a start signal (118), produced in response to a read command (112), is passed through a delay circuit (132) slaved with the delay lock loop (120) so that the read clock signal (129) and a delayed start signal (174) are subject to the same internal timing variations. The delayed start signal (174) is used to thereby control the output of read data by the read clock signal (129).