| 摘要 |
A method, system and processor are provided for minimizing latency and loss of processor bandwidth in a pipelined processor when responding to an interrupt. The method advantageously avoids emptying and refilling the processor's instruction pipeline in order to service an interrupt request. Instead, a short sequence of instructions comprising the interrupt response is inserted into the pipeline. Normal pipeline operation stalls while the inserted instructions execute, but since flow is not disrupted the loss in bandwidth is not as great as if the pipeline were flushed. Furthermore, direct insertion of the instructions into the pipeline avoids the need for the processor to save its context and branch to an interrupt service routine in memory; this results in much faster response in servicing the interrupt, thereby reducing latency. In the preferred embodiment, the method applies to a pipelined processor having a RISC (Reduced Instruction Set Computer) architecture, which receives interrupt requests from one or more DMA memory controllers. The instructions inserted into the pipeline compute block address information for a DMA transfer. A system and processor implementing the method are disclosed, based on an enhancement of a conventional RISC processor design, and making use of registers and other existing logic resources within the processor. It is shown that the enhanced processor can respond to DMA interrupts with shorter latency and a smaller reduction in processor bandwidth than if conventional interrupt handling were used.
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