发明名称 Aggressive capacitor array cell layout for narrow diameter DRAM trench capacitor structures via SOI technology
摘要 A method of increasing DRAM cell capacitance via formation of deep, wide diameter trench capacitor structures, has been developed. An underlying semiconductor substrate is used to accommodate deep, wide diameter trench capacitor structures while an overlying, bonded, thinned semiconductor substrate is used to accommodate narrow diameter trench structures, in turn used for communication to the underlying deep trench capacitor structures, as well as to accommodate the elements of the DRAM device, such as the transfer gate transistors. The use of an underlying semiconductor substrate for accommodation of the trench capacitor structures allows a wider diameter structures to be used, thus reducing patterning difficulties encountered when forming narrow diameter, deep trench capacitor structures.
申请公布号 US6703273(B2) 申请公布日期 2004.03.09
申请号 US20020043477 申请日期 2002.01.11
申请人 PROMOS TECHNOLOGIES, INC. 发明人 WANG HSIAO-LEI;CHENG CHAO-HSI (JESSE);LIAO HUNG-KWEI
分类号 H01L21/334;H01L21/8242;H01L27/108;H01L29/94;(IPC1-7):H01L21/824 主分类号 H01L21/334
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