| 摘要 |
<p>PROBLEM TO BE SOLVED: To realize the phase synchronization of a clock signal from each frequency divider with a simple circuit constitution. SOLUTION: Plural synchronizing devices for performing the phase synchronization of plural clock signals outputted from plural frequency-dividers 3a, 3b, 3c and 3d which respectively frequency-divide an input clock are provided with plural phase detecting circuits 6, 7, 8, 15a, 15b, 16a, 16bg and 17 which respectively detect the phase matching/mismatching of each clock signal with a previously decided reference clock among the plural clock signals outputted from the plural frequency dividers, and output the phase matching/nonmatching as a detected result, plural reset signal generating circuits 10 which respectively transmit a reset signal to the frequency-divider which outputs the clock signal corresponding to the detected result outputted by each phase detecting circuit indicating the phase nonmatching in order to restart the frequency divider, and plural gate circuits 11 and 12 which respectively reinput the detected result outputted from the phase detecting circuits to the reset signal generating circuit after the lapse of a fixed time after the reset signal is transmitted from the reset signal generating circuit.</p> |
