| 摘要 |
<P>PROBLEM TO BE SOLVED: To achieve a shift register that operates normally even if the amplitude of a clock signal is small, and has a small amount of power consumption. <P>SOLUTION: A level shifter 13 for boosting the voltage of the clock signal CK is provided for each SR flip-flop F1 for composing the shift register 11. As a result, after the voltage of the clock signal is boosted by only one level shifter, the transmission distance of the boosted clock signal can be reduced as compared with the transmission to each flip-flop, and hence a load capacity in the level shifter 13 can be reduced. Additionally, each level shifter 13 operates while the level shifter 13 at the first stage is outputting a pulse and stops the operation when the pulse output is completed, thus achieving operation only when supplying the clock signal CK to the corresponding to SR flip-flop F1 is required. Therefore, the power consumption in the shift register operating normally can be reduced even if the amplitude of the clock signal is small. <P>COPYRIGHT: (C)2004,JPO |
