| 摘要 |
A self-timed transmission system and method efficiently communicate a plurality of data operands successively through common digital device, for example, a shifter, bus network, multiplexer, or buffer, in a self-timed manner in order to minimize hardware requirements. Although not limited to this particular application, the self-timed transmission system and method are particularly suited for implementation in connection with shifting operations in a floating point (FP) fused multiply adder of a high performance microprocessor. The self-timed transmission system is constructed as follows. An encoder encodes first and second data operands that are each defined on separate respective first and second sets of logic paths onto the same third set of logic paths by changing the encoding scheme. The first and second data operands are mathematically related, making this re-encoding process possible. A device, for example, a shifter, bus network, multiplexer, or buffer, processes the first and second data separately, successively in time, and in a self-timed manner, and communicates the processed first and second data onto a fourth set of logic paths. A decoder receives the processed first and second data in succession from the device on the fourth set of logic paths. The decoder decodes the first and second data onto separate respective fifth and sixth sets of logic paths, which have an encoding that corresponds to the original first and second sets of logic paths.
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