| 摘要 |
<p>The invention relates to a method for eliminating routing congestion (81) in an integrated circuit (IC) layout defined by a placement plan (72, 75) indicating a position within the layout of each cell forming the IC and routing plan (73, 77, 79) describing routes followed by nets interconnecting the cells. Routing congestion is eliminated by estimating routing congestion in various areas of the layout and relocating each cell to least routing congested areas of the layout (83) for which cell relocation results in a reduction in the total lengths of the nets connected to the cell that exceeds a predetermined minimum reduction.</p> |
