发明名称 |
Processor with demand-driven clock throttling power reduction |
摘要 |
A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down. |
申请公布号 |
US2004044915(A1) |
申请公布日期 |
2004.03.04 |
申请号 |
US20020187698 |
申请日期 |
2002.07.02 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORTATION |
发明人 |
BOSE PRADIP;CITRON DANIEL M.;COOK PETER W.;EMMA PHILIP G.;JACOBSON HANS M.;KUDVA PRABHAKAR N.;SCHUSTER STANLEY E.;RIVERS JUDE A.;ZYUBAN VICTOR V. |
分类号 |
G06F1/04;G06F1/32;G06F9/38;(IPC1-7):G06F1/32 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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