Semiconductor memory device internally generating internal data read timing

摘要

A dummy circuit including a plurality of dummy cells is provided in correspondence to a predetermined number of word lines. When either one of corresponding word lines are selected, a dummy bit line equal in load to a normal bit line is driven using the plurality of dummy cells included in this dummy circuit. A potential of this dummy bit line is detected by a dummy sense amplifier, and a sense enable signal is generated. Therefore, it is possible to accurately detect a sense timing irrespectively of array architecture.