| 摘要 |
<P>PROBLEM TO BE SOLVED: To acquire an efficient S/N (signal to noise ratio) in first to third reference frequency clocks each having predetermined ratio in relation to a certain reference clock by using a PLL circuit in spite of limitations in the S/N of noise floor. <P>SOLUTION: The first reference frequency clock is inputted to a first PLL circuit as the reference clock, and an intermediate frequency clock having a first predetermined ratio in relation to the reference clock is generated. The intermediate frequency clock is inputted to a second PLL circuit and a third PLL circuit. The second reference frequency clock having a second predetermined ratio in relation to the reference clock is generated, and the third reference frequency clock having a third predetermined ratio in relation to the reference clock is generated. <P>COPYRIGHT: (C)2004,JPO |
