DATA TRANSFER DEVICE

摘要

PROBLEM TO BE SOLVED: To obtain a data transfer device that eliminates the needs for an asynchronism countermeasure and skew matching at data transfer in reception or transmission between a high-speed operation block and a low-speed operation block.

SOLUTION: This high-speed operation block 1 is provided with: a shift register 12 for performing serial data/parallel data conversion on the basis of a load enable signal ld en; a clock generation block 17 for generating a clock CLK B having a cycle which is an integer-multiple of a clock CLK A in accordance with the count value of the clock CLK A; and a sampling circuit 15 for generating the load enable signal ld en having the same cycle as that of the clock CLK B in accordance with the count value of the CLOCK A and supplying the load enable signal ld en to the shift register 12.

COPYRIGHT: (C)2004,JPO