| 摘要 |
An instruction cache is disclosed, which comprises an instruction cache control circuit, an instruction cache tag memory, an instruction cache data memory, and an instruction cache tag access control circuit which is provided between the instruction cache control circuit and the instruction cache tag memory, which monitors whether or not an instruction cache tag memory address in an accesses from the instruction cache control circuit to the instruction cache tag memory is the same as that in a previous access from the instruction cache control circuit to the instruction cache tag memory, without being supplied with a non-jump instruction detecting signal from the instruction cache control circuit, and which controls whether or not access to the instruction cache tag memory is possible in accordance with a result of the monitor.
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