发明名称 SELF-SYNCHRONIZING FIFO MEMORY DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a self-synchronizing FIFO (First In First Out) memory device which can substantially increase a physical memory capacity without increasing the delay time and can process two asynchronous requests of writing and reading in parallel. SOLUTION: The self-synchronizing FIFO memory device 100 has a structure lined up with n pieces of self-synchronizing data transmission lines 111 to 11n in parallel. An input control section 101 selects one among n pieces of the self-synchronizing data transmission lines and mediates the hand-over of a first transfer request signal, a first acknowledge (transfer instruction) signal and data between the selected self-synchronizing data transmission line and the self-synchronizing data transmission line of a previous stage. Also, an output control section 102 selects one among n pieces of the self-synchronizing data transmission lines and mediates the hand-over of a second transfer request signal, a second acknowledge (transfer instruction) signal and data between the selected self-synchronizing data transmission line and the self-synchronizing data transmission line of a post stage. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004071103(A) 申请公布日期 2004.03.04
申请号 JP20020231787 申请日期 2002.08.08
申请人 SHARP CORP 发明人 MURAMATSU GOJI;YAMANAKA SHUICHI;TOKURA ATSUSHI;URATA TAKUJI
分类号 G11C7/00;G06F5/08;G06F7/00;G11C8/02;(IPC1-7):G11C7/00 主分类号 G11C7/00
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