发明名称 Clock generator for generating an accurate and low-jitter clock
摘要 <p>A clock generator has a clock generating circuit (5), a phase difference detection circuit (1, 7), and a control signal generating circuit (3, 4, 9). The clock generating circuit has a function for varying a clock phase in accordance with a control signal. The phase difference detection circuit compares the clock phase output from the clock generating circuit with a phase of a reference waveform, and detects a phase difference therebetween. The control signal generating circuit generates a control signal for controlling the clock phase of the clock generating circuit, based on phase difference information obtained from the phase difference detection circuit. The phase difference detection circuit has a plurality of phase detection units. At least one of the plurality of phase detection units carries out a direct phase detection in which a phase of the clock is directly compared with the phase of the reference waveform, and at least the other one of the plurality of phase detection units carries out an indirect phase detection using a phase-synchronized waveform generating circuit (6) generating a waveform synchronized in phase with the reference waveform or an output of the clock generating circuit and a phase information extracting circuit extracting phase information from the phase-synchronized waveform. &lt;IMAGE&gt;</p>
申请公布号 EP1394949(A1) 申请公布日期 2004.03.03
申请号 EP20030254586 申请日期 2003.07.23
申请人 FUJITSU LIMITED 发明人 TAMURA, HIROTAKA
分类号 G06F1/08;G06F1/04;H03L7/07;H03L7/081;H03L7/087;H03L7/089;H03L7/091;H03L7/093;H04L7/033;(IPC1-7):H03L7/087 主分类号 G06F1/08
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