A scalable flash eeprom memory cell, method of manufacturing and operation thereof

摘要

A scalable flash EEPROM cell has a semiconductor substrate (12) with a drain (16) and a source (14) and a channel (18) therebetween. A select gate (20) is positioned over a portion of the channel and is insulated therefrom. A floating gate (24) has a first portion (26) over the select gate and insulated therefrom, and a second portion (28) over a second portion of the channel and over the source, and is between the select gate and the source. A control gate (30) is over the floating gate and is insulated therefrom. A memory array using this memory cell is also disclosed.