发明名称 |
DIGITAL CIRCUIT HAVING A DELAY CIRCUIT FOR CLOCK SIGNAL TIMING ADJUSTMENT |
摘要 |
<p>A digital circuit according to the present invention includes a pulse delay circuit where a driving current of an inverter is variable, for causing timing of a clock signal to be variable; and the pulse delay circuit has a stabilizing circuit for an amount of a pulse delay by a delay synchronizing loop, and a generating circuit for a pulse delay amount setting voltage with nonlinear characteristics. The present invention makes it possible to realize a timing delay circuit with high resolution, which is not influenced by an operating environment and requires only a small area for the circuit. <IMAGE></p> |
申请公布号 |
AU2003246277(A1) |
申请公布日期 |
2004.03.03 |
申请号 |
AU20030246277 |
申请日期 |
2003.07.08 |
申请人 |
NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY |
发明人 |
EIICHI TAKAHASHI;YUJI KASAI;TETSUYA HIGUCHI |
分类号 |
G06F1/10;G06F1/04;H03K5/00;H03K5/13;H03L7/07;H03L7/081;(IPC1-7):H03K5/13 |
主分类号 |
G06F1/10 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|