| 摘要 |
1,039,045. Pulse modulation; transistor pulse circuits. SIEMENS & HALSKE A.G. Aug. 23, 1963 [Aug. 27, 1962; Jan. 28, 1963], No. 33391/63. Headings H3T and H4L. A circuit for transforming a voltage into a pulse train of frequency dependent on the voltage is provided with means for suppressing the pulse output if the frequency drops below a predetermined level. In Fig. 1 the voltage at terminals K1, K2, determines the frequency of the pulse output at terminals K3, K4. The pulses pass to two AND gates G1 and G2 and to a mono-stable device M1, the recovery time of which corresponds to the lower limit of pulse frequency below which the pulses are to be blocked. If the device M1 has not had time to recover, gate G1 will be open on the occurrence of the next pulse and a second similar monostable device M2 will be actuated. The pulses from M1 and M2 passing through OR gate G3 will maintain AND gate G2 open and the signal pulses will pass through to the utilization circuit A. If Ml has time to recover, gate G1 is closed when the next pulse arrives so M2 is not actuated; the pulses from M1 open gate G2 only in the intervals between pulses, so low frequency pulses do not pass to the output. In another circuit, Fig. 3, input pulses at point E pass through transistor T1 to Diode D and to transistor T2. On receipt of a pulse T2 conducts and discharges condenser C which then starts charging through resistance R. If sufficient time elapses before the next pulse, condenser C charges sufficiently to cause T3 to conduct and cut off T4. With T4 cut-off the diode D is biased so as to be non-conducting and pulses do not pass to the output. The transistors used in Fig. 3 are of the PNP type. In a modification, Fig. 5 (not shown), transistors T2 and T3 are replaced by NPN transistors, and transistor T3 controls the bias on diode D. |
