Floor plan tester for integrated circuit design

摘要

A method of testing a floor plan for an integrated circuit prior to resynthesis includes attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has an unreachable pin; and if the least-penalty path is constructed, then attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has a bottleneck.