发明名称 |
Pre-decoder for glitch free word line addressing in a memory device |
摘要 |
A reset circuit in a memory device applies a reset to the global X-address latch and the local X-address latch. This resets those latches and effectively de-addresses all word lines prior to application of the next address. This eliminates any overlap of main word line signals between successive addresses thereby eliminating a possible glitch that would cause simultaneous word line addressing and potentially a memory read or write error. By terminating the addressing, the address cycle time may be reduced.
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申请公布号 |
US6700822(B1) |
申请公布日期 |
2004.03.02 |
申请号 |
US20020146451 |
申请日期 |
2002.05.15 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY |
发明人 |
WANG TAO-PING |
分类号 |
G11C8/10;G11C16/08;(IPC1-7):G11C16/04 |
主分类号 |
G11C8/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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