| 摘要 |
The present invention provides a high-speed processing and high precision delay calculation method of semiconductor integrated circuit devices having a plurality of cells and interconnections connecting therebetween, with less data to be obtained prior to delay calculation. The method comprises the steps of: calculating temporary delay T0 that is the delay of the cell on the basis of total load capacitance Ct of the capacitance values connected to the output of the cell; calculating the voltage Vc at the node connected to the load capacitance C connected to the output of the cell at the temporary delay T0; calculating effective load capacitance Ceff by multiplying the ratio of the voltage Vc to the voltage Vtb defining the delay with the capacitance C; calculating the cell delay Tc on the basis of the effective load capacitance Ceff.
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