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发明名称
半导体积体电路装置
摘要
本发明系提供一种半导体积体电路装置,其系藉由将层间绝缘膜之第1配线层之配线间空间予以紧密化,而增加层间绝缘膜之第1配线层之总量,并减低造成弯曲的原因之低硬度层间绝缘膜之总量。其结果,例如在设置于层间绝缘膜上之保护膜,系由于并不产生会导致该层间绝缘膜弯曲的应力(荷重等),故在其保护膜不致于产生龟裂等之现象。因此,能防止起因于上述的保护膜之龟裂等之第2配线层之断线等之不适合之情形,并可构成可靠性较高之半导体积体电路装置。
申请公布号
TW200403020
申请公布日期
2004.03.01
申请号
TW092109086
申请日期
2003.04.18
申请人
夏普股份有限公司
发明人
铃木岳洋
分类号
H01L
主分类号
H01L
代理机构
代理人
陈长文
主权项
地址
日本
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