| 摘要 |
PROBLEM TO BE SOLVED: To improve reliability and a manufacturing yield in multilayer interconnection by forming a wiring groove so that no crown fences are generated around a via hole, and by protecting lower layer wiring from a damage due to the etching of a process for forming the via hole and wiring groove. SOLUTION: After the lower layer wiring 13 is subjected to patterning to a first interlayer insulating film 12 on a semiconductor substrate 11, an etching stop layer 14, a second interlayer insulating film 15, and a reflection preventing film 16 are successively built up. Then, a hole section 15a and a wiring groove 15b are successively subjected to patterning to the second interlayer insulating film 15. At this time, an etching condition for preventing the lower layer wiring 13 from being exposed is set for forming a recess 14a in the etching stop layer 14. Then, the etching stop layer 14 positioned at the lower side of the hole section 15a is removed, and the lower layer wiring 13 is exposed for forming a via contact 20a and upper layer wiring 20b. COPYRIGHT: (C)2004,JPO |
