| 摘要 |
PROBLEM TO BE SOLVED: To provide a layout method for a large-scale circuit that obtains the most adequate layout considering timing and wiring congestion degree of a logic device to be designed, when an LSI logic device is designed. SOLUTION: When the layout of a logic circuit, wiring and so on in a large-scale integrated circuit is designed, a net list, which represents connection relations of logic circuit layout information, wiring information and so on, and timing restrictions are read in (S1 and S2), a high fanout net, in which the number of output fanout of each logic circuit becomes high fanout, is extracted from the net list (S3), the layout of the logic circuit is performed by timing-driven layout method on the basis of the read information on the net list and timing restrictions (S6), load distribution is executed to the extracted high fanout net in consideration of the layout of the logic circuit (S7), and a clock tree is established to the output of each logic circuit (S8), and then load-distributed and optimal layout is obtained. COPYRIGHT: (C)2004,JPO
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