发明名称 Automatic status assignment logic circuit apparatus for bay devices
摘要 In accordance with the present invention, the circuit apparatus has a first and a second connection point each for respectively connecting to the first bay and second bay for communicating with them to determine which device in the bays is the master device. The circuit apparatus also has a third and a fourth connection point both of them for connecting to the first bay or second bay for receiving the Boolean algebra to determine which device is the master device. The circuit apparatus further has a fifth connection point for determining whether the circuit apparatus works.
申请公布号 US2004039858(A1) 申请公布日期 2004.02.26
申请号 US20020225161 申请日期 2002.08.22
申请人 QUANTA COMPUTER INC. 发明人 YU CHEN-YO;WU CHUN-HSIEN
分类号 G06F13/38;(IPC1-7):G06F13/00 主分类号 G06F13/38
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