发明名称 Spare input/output buffer
摘要 An integrated circuit ("IC") package includes an input/output ("I/O"), a spare I/O circuit, and a resident IC for processing data. The I/O circuit is coupled with a plurality of external pins, which provide external electrical connections for the communication of data and information between the resident circuitry and external circuits, such as system logic and other electronic devices to which the IC package is coupled. The I/O circuit provides a data path between the I/O pins and the resident IC. The I/O circuit may include a data buffer and voltage and current surge protection to the IC package. The resident IC includes the primary IC electronic components, such as latches, gates, and processors, configured to process the data. The spare I/O circuit provides a redundant connection between the resident IC and the external circuits. The spare I/O circuit may be provided integral to the IC package and is configured to couple a selected data I/O of the resident IC with the NC pin, and thereby bypass the I/O path provided by the I/O circuit. The spare I/O buffer may be programmed to select the I/O of the resident IC to be bypassed to the NC pin. Where the IC package includes multiple NC pins, the spare I/O buffer may provide redundant I/O path to each NC pin provided with the IC package.
申请公布号 US2004039863(A1) 申请公布日期 2004.02.26
申请号 US20020226697 申请日期 2002.08.23
申请人 ISOM MELVIN T.;HEGDE SHAILESH U. 发明人 ISOM MELVIN T.;HEGDE SHAILESH U.
分类号 G06F13/14;H01L23/50;H01L23/58;(IPC1-7):G06F13/14 主分类号 G06F13/14
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