发明名称 METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE
摘要 PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor package which can shorten the length of a circuit pattern extending from a via hole formed nearby the outer circumferential end of the package to the outer circumferential end of the package as much as possible, and can form a metal layer for bonding the circuit pattern. SOLUTION: A multilayer circuit board C is used which has the circuit pattern having one end positioned inside the outer circumferential edge and the other end exposed in a cavity 14, after sealing substrates 24 and 24 are laminated on both the surface sides of the multilayer circuit board C to seal the cavity 14. A via hole 18 which electrically connects with an end of the circuit pattern nearby the outer circumferential edge of the multilayer circuit board C is formed through the sealing substrates 24 and 24 then a metal layer is formed at the other end of the circuit pattern which is exposed in the cavity 14 by electrolytic plating using as an electrification layer a metal layer 28 electrically connected to the through via hole 18 to form a bonding part. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004063577(A) 申请公布日期 2004.02.26
申请号 JP20020216897 申请日期 2002.07.25
申请人 SHINKO ELECTRIC IND CO LTD 发明人 TANAKA SHOICHI
分类号 H01L23/12;(IPC1-7):H01L23/12 主分类号 H01L23/12
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