Semiconductor storage device including random access memory cells having a plurality of indendently accessible access ports

摘要

A dual port DRAM cell of a memory cell array circuit (110) has two ports, each connected to a bit line. The bit line is of open-bit-line configuration and is connected to a sense amplifier. An access circuit (150A) and an access circuit (150B) access to memory cells via one port and the other port, respectively. When the access circuit (150A) accesses to the memory cell, the sense amplifier amplifies the potential of the bit line connected to the access-object cell. During this amplification period, the access circuit (150A) outputs a control signal (WLONA). The access circuit (150B) receives the control signal (WLONA) and operates so as not to change, during the amplification period, the potential of a bit line adjacent to the bit line that is in the amplification period and is used by the access circuit (150B) at the time of access.