STRUCTURE AND METHOD FOR MANUFACTURING BURIED DRAM BY SOI WITH PATTERN HAVING VERTICAL DEVICE CELL

摘要

PROBLEM TO BE SOLVED: To provide a silicon-on-insulator (SOI) method with a pattern for manufacturing a composite integrated circuit having both of a logic circuit part and a buried dynamic random access memory (DRAM) array part.

SOLUTION: The method includes a step to form a buried oxide layer BOX at the logic circuit part 18 of a substrate, which is not masked by a first mask, by injecting oxygen and a step to apply etching to isolation trenches inside the array part 17 and the logic circuit part 18 by a second mask. The first mask can additionally protect the array part 17 when the corners of the device inside the logic circuit part 18 are rounded. The second mask can additionally protect the logic circuit part 18 when the injection inside the array part 17 is executed. A DRAM cell is formed on a bulk part of the substrate in a state of including at least one SOI device having the round corners and at least one DRAM cell having a vertical path gate.

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