SELF-ALIGNED VERTICAL TRANSISTOR DRAM STRUCTURE AND ITS MANUFACTURING METHODS

摘要

A self-aligned vertical transistor DRAM structure comprising a self-aligned trench structure and a self-aligned common-drain structure are disclosed by the present invention, in which the self-aligned trench structure comprises a deep-trench capacitor region having a vertical transistor and a second-type shallow-trench-isolation region being defined by a spacer technique and the self-aligned common-drain structure comprises a common-drain region being defined by another spacer technique. The self-aligned vertical transistor DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common-drain conductive bit-lines.