发明名称 |
Circuit and method for reading data transfers that are sent with a source synchronous clock signal |
摘要 |
A circuit and method for reading data transfers that are sent with a source synchronous clock signal. The circuit has a data input for receiving data signals carrying data being transferred, a clock input for receiving synchronous clock signals, and a delay circuit connected to the clock input for generating a delayed clock signal which is delayed from said synchronous clock signal a predetermined time period. The circuit also includes a pipeline connected to the data input for sampling the data on the data input in response to said delayed clock signal thereby stretching the sampling of incoming data.
|
申请公布号 |
US2004037158(A1) |
申请公布日期 |
2004.02.26 |
申请号 |
US20020225871 |
申请日期 |
2002.08.22 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
COTEUS PAUL W.;FERRAIOLO FRANK D.;GOWER KEVIN C. |
分类号 |
G11C7/10;(IPC1-7):G11C8/00 |
主分类号 |
G11C7/10 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|