发明名称 Method for forming a metal interconnection layer of a semiconductor device using a modified dual damascene process
摘要 A method for forming a metal interconnection layer of a semiconductor device comprises forming a film including a material selective to a medium used in an ashing process on an interlayer insulating film. The method comprises transforming the film during the ashing process to form an interconnection pattern having a dual damascene structure. A dielectric material such as copper is deposited on the interconnection pattern, which is planarized through CMP, thereby forming a via contact having a single damascene structure without a recess therein.
申请公布号 US2004038521(A1) 申请公布日期 2004.02.26
申请号 US20030449973 申请日期 2003.05.30
申请人 SAMSUNG ELECTRONICS., LTD. 发明人 KIM JAE-HAK;LEE SOO-GEUN;LEE KYUNG-WOO
分类号 H01L21/28;H01L21/768;(IPC1-7):H01L21/476;H01L21/44 主分类号 H01L21/28
代理机构 代理人
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