| 摘要 |
<P>PROBLEM TO BE SOLVED: To avoid problems derived from a high aspect ratio encountered in a conventional hole by providing a fabrication process of a trench capacitor. <P>SOLUTION: First electrode plate of a memory cell is disposed on the circumferential edge at the lower surface part of an insular semiconductor structure in a substrate, a second electrode plate is disposed in the surface at the lower surface part of the insular semiconductor structure and in the surface of the substrate on the outside of the insular semiconductor structure, and a capacitor dielectric layer 112 is interposed between the second electrode plate and the first electrode plate. Furthermore, a transistor for controlling the trench capacitor C is disposed on the island-like semiconductor structure and that transistor is provided with a first source/drain 123, a second source/drain 124 and a gate electrode G. Furthermore, an embedded strap 126 is interposed between the second source/drain and the first electrode plate, and a conductive plug 134 is interposed between the first source/drain and a bit line B. <P>COPYRIGHT: (C)2004,JPO |
