发明名称 |
Computer apparatus and bus control scheme |
摘要 |
A continuous data server includes a storage unit connected to a buffer memory which is in turn connected to a plurality of communication control units which transfer data of the buffer memory to a network. The right to use a bus interconnecting the buffer memory and communication control units is deterministically assigned by a micro-scheduler in accordance with a program stored in a micro-schedule table. The micro-scheduler allocates the right to use the bus in accordance with a predetermined schedule, rather than by arbitration. <IMAGE> |
申请公布号 |
EP0797151(B1) |
申请公布日期 |
2004.02.25 |
申请号 |
EP19970301829 |
申请日期 |
1997.03.18 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
ASANO, SHIGEHIRO;MASAKI, SUZUKI |
分类号 |
G06F13/16;G06F12/06;G06F13/00;G06F13/362;G06F13/372;H04Q11/04 |
主分类号 |
G06F13/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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