摘要 |
<p>A processor (50) operable in response to an instruction set comprising a plurality of instructions. The processor comprises a functional unit (52) comprising an integer number S of sub-units (541, 542, 543), wherein S is greater than one. Each of the sub-units is operable to execute, during an execution cycle, at least one of the instructions in the instruction set in response to at least two data arguments (A, B). The processor further comprises circuitry (58A1, 58A2, 58A3, 58B1, 58B2) for providing an updated value of the at least two data arguments to less than all S of the sub-units for a single execution cycle. <IMAGE></p> |