发明名称 |
Instruction cache way prediction for jump targets |
摘要 |
Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way prediction scheme lies in its efficiency when dealing with instructions that vary the PC in a non-sequential manner, such as branch instructions including jump instructions. To facilitate caching of non-sequential instructions an additional cache way prediction memory is provided to deal with the non-sequential instructions. Thus during program execution a decision circuit determines whether to use a sequential cache way prediction array or a non sequential cache way prediction array in dependence upon the type of instruction. Advantageously the improved cache way prediction scheme provides an increased cache hit percentage when used with non-sequential instructions. |
申请公布号 |
AU2003251093(A8) |
申请公布日期 |
2004.02.25 |
申请号 |
AU20030251093 |
申请日期 |
2003.08.11 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V. |
发明人 |
JAN-WILLEM VAN DE WAERDT |
分类号 |
G06F9/38;G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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